Method of storing information on an optical disc

ABSTRACT

A method is described for writing information to a record medium ( 2 ). 152 code words [ 11 (j)] each having 248 bytes [mI(ij)] and 12 BIS words each having 62 BIS bytes [b2(r,s)] are combined to form an ECC block (M 3 ) having 38 440 elements [m3(v,w)], which elements are consecutively written. Also, a method is described for reading information from a record medium ( 2 ). An ECC block (M 3 ) having 38 440 elements [m 3 (v,w)] is read, from which 152 code words [ 11 (j)] each having 248 bytes [ml(ij)]and 12 BIS words each having 62 BIS bytes [b 2 (r,s)] are reconstructed.

FIELD OF THE INVENTION

The present invention relates in general to a method of storinginformation on an optical disc. More specifically, the present inventionrelates to a storage method where information is stored in the form ofECC blocks. Also, the present invention relates to a method of readinginformation from such disc.

Further, the present invention relates to a disc drive apparatus forwriting/reading information into/from an optical storage disc;hereinafter, such a disc drive apparatus will also be indicated as“optical disc drive”.

BACKGROUND OF THE INVENTION

As is commonly known, an optical storage disc comprises at least onetrack, either in the form of a continuous spiral or in the form ofmultiple concentric circles, of storage space where information may bestored in the form of a data pattern. Optical discs may be of theread-only type, where information is recorded during manufacture, whichinformation can only be read by a user. The optical storage disc mayalso be of a writable type, where information may be stored by a user.Such disc can be of a write-once type, which can only be written once,or of a rewritable type, which can be written many times. The presentinvention relates, in principle, to all types of discs, but will beexplained specifically, by way of example; with respect to rewritablediscs, although this example should not be considered as limiting thescope of the invention to this field. Since the technology of opticaldiscs in general, the way in which information can be stored in anoptical disc, and the way in which optical data can be read from anoptical disc, is commonly known, it is not necessary here to describethis technology in more detail.

When storing information on a record medium, the information is coded indata words in accordance with a predetermined format. For differentapplications, different formats exist. One general problem is that, onwriting and/or on reading, errors may occur, so that the data read backfrom a recording is not identical to the original data This isundesirable. Therefore, error-correction schemes have been developed,capable of correcting data errors to a certain extent. Sucherror-correction schemes involve the addition of error correction bitsto the original data. In a particular class of error-correction schemes,a predefined amount of original data and error-correction bits are mixedtogether, according to a predefined algorithm. The combination forms anError Correction Code block (ECC block).

Since coding schemes for ECC blocks are known to those skilled in theart, while furthermore the present invention is not related to thecoding scheme as such, a detailed discussion of a coding algorithm willbe omitted here. By way of example, reference is made to the DVDstandard ECMA 267: “120 mm DVD - Read Only Disc”, December 1997, Section4 “Data Format”. Also, reference is made to U.S. Pat. Nos. 6.367.049 and6.378.100 to Van Dijk et al, who describe a method for encodingmultiword information.

Basically, an ECC block comprises a predetermined number of code words,each code word having a predetermined length, i.e. comprising apredetermined number of data bytes and a predetermined number of errorcorrection bytes. Thus, the ECC block can be considered as a collectionof code words. When the ECC block is written to a storage medium, theindividual bytes of the code words of one ECC block are written in apredetermined order, such that bytes of one code word are physicallylocated at relatively large distances from each other. On reading fromthe storage medium, code words can only be decoded if the full code wordis reconstructed by putting all bytes of this code word in the rightorder. The distribution of the individual bytes on the storage medium issuch that, even if it is desired to decode one code word only, theentire ECC block must be read.

It is to be appreciated that the robustness of the ECC coding depends onthe ratio of the number of error correction bytes to the number of databytes: the more error correction bytes a code word comprises, the moreerrors can be corrected, but the trade-off is that the data capacity ofthe code word is reduced. In any event, if the number of errorcorrection bytes is fixed, the maximum number of errors that can becorrected in one code word is also fixed. If the actual number of errorsin one code word exceeds said maximum, the code word as a whole cannotbe decoded without error. This will be indicated as the errorsensitivity of an ECC block: the lower the sensitivity, the more errorsare correctable.

There is a trend towards reducing physical dimensions of data storageequipment. Recently a disc drive for small discs (SFFO) was developed,suitable for implementation in mobile equipment such as a mobiletelephone, Personal Digital Assistant (PDA), etc. The standard for SFFOis still under development. When developing a new standard, it isadvantageous if such a new standard can be based as much as possible onan existing standard, because encoders and decoders for use in the newstandard may then be based on the encoder and decoder technology alreadydeveloped for the existing standard. One potentially suitable standardto be used as a basis for the SFFO standard is Blu-Ray Disc (indicatedhereinafter as BRD), and the present invention has been devised againstthe background of the BRD standard.

In the BRD standard, an ECC block has a size of 64 kBytes (data bytes).When written on disc, such a block occupies approximately 71 mm of tracklength. The smallest track, i.e. the inner track, in BRD has a radius of24 mm, hence a length of about 150 mm, which is longer than the tracklength occupied by one 64-kByte ECC block.

An SFFO disc has an inner track radius of about 6 mm, hence the lengthof the inner track is about 38 mm, which is smaller than the tracklength occupied by one 64-kByte ECC block. In other words, if theexisting BRD standard were used in this case, the ECC blocks wouldoccupy about two adjacent 360° track portions in the inner regions ofthe SFFO disc.

Such a situation would increase the error sensitivity of an ECC block,at least in respect of certain types of errors.

A first example is a burst error, i.e. relatively large errors which areusually associated with mechanical irregularities of the disc, such as aparticle of dirt, a fingerprint, a scratch, etc. Such mechanicalirregularities typically have a physical size larger than the distancebetween two adjacent tracks, such that it is practically certain that aburst error will affect two or more adjacent tracks. In a case where anECC block would extend over two adjacent tracks, one burst error wouldcause two errors within the same ECC block: the part of the ECC blockdamaged by one burst error is now twice as large.

A second example is a random error, i.e. errors which are quite smallbut nevertheless large enough as to possibly affect two neighbouringtracks. Now, in a case where an ECC block extends over two adjacenttracks, it may happen that, at a certain radius, two bytes of one andthe same code word are aligned, i.e. located next to each other inadjacent tracks. In such a case, a random error, small as it is, maynevertheless affect such two bytes of one word, i.e. cause two errors inone word. Furthermore, the standard interleaving procedure of BRD issuch that, if two bytes of one code word align, it is highly likely thatthe same applies to more pairs of bytes of the same code word, whilefurthermore it is highly likely that the same applies to more code wordsof the same ECC block.

The main objective of the present invention is to overcome saidproblems, or at least to reduce the error sensitivity of ECC blocks.

SUMMARY OF THE INVENTION

In order to alleviate at least some of said problems associated withreducing the radius of record tracks of record discs, the presentinvention proposes to use ECC blocks having a size of 32 kB. Comparedwith 64-kB ECC blocks, the physical length of a track occupied by suchan ECC block is reduced by a factor 2, resulting in a length of about 36mm, i.e. less than one 360° track portion.

It is noted that, when the size of an ECC block is reduced by a factor 2, the maximum size of a burst error that can be corrected is alsoreduced by a factor 2 . However, with respect to random errors, thecorrection capacity for 32-kB blocks is the same as for 64-kB blocks.Therefore, even if a random error were to cause two errors in twoconsecutive 32-kB blocks, these two errors would always occur in twodifferent code words, i.e. such a random error will now only cause oneerror per code word. Thus, basically, the sensitivity of each 32-kBblock to a random error is the same as the sensitivity of a 64-kB blockto such a random error.

It is, of course, possible to develop a new standard on the basis of32-kB ECC blocks. However, this is not preferred: it is preferred tomaintain the BRD standard as much as possible. To meet this aim, thepresent invention proposes a method of calculating 32-kB ECC blocksusing the BRD standard for 64-kB ECC blocks as a starting point.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other aspects, features, and advantages of the presentinvention will be further explained by the following description of apreferred embodiment of the present invention with reference to thedrawings, in which same reference numerals indicate same or similarparts, and in which:

FIG. 1 schematically shows relevant components of an optical disc drive;

FIG. 2 illustrates a digital data stream;

FIG. 3 illustrates a code word of 248 bytes;

FIG. 4 illustrates a primary matrix;

FIG. 5 illustrates a secondary matrix;

FIG. 6 schematically illustrates the secondary matrix after a row shift;

FIG. 7 schematically illustrates the matrix after insertion ofBIS-columns;

FIG. 8 schematically illustrates the writing of block segments;

FIG. 9 schematically illustrates the effect of a random error;

FIG. 10 schematically illustrates a secondary matrix according to theinvention;

FIG. 11 schematically illustrates this matrix after a cyclic row shiftoperation;

FIG. 12 schematically illustrates this matrix after insertion of BIScolumns;

FIG. 13 schematically illustrates the writing of bytes as blocksegments;

FIG. 14 schematically illustrates the effect of a random error; and

FIG. 15 schematically illustrates an embodiment of a process ofcalculating a 155×248 matrix.

DESCRIPTION OF THE INVENTION

In the following, the notation z(x)=MOD(x,y) will be used to indicate afunction of x resulting in a value z in the range 0≦z≦(y-1) bysubtracting n*y from x if x>0 or adding n*y to x if x<0, n being aninteger.

Further, the notation z=DIV(x,y) will be used to indicate the divisionfunction where x is divided by y (i.e. x/y), the result to be roundeddown to the nearest integer.

FIG. 1 schematically shows relevant components of an optical disc drive1 capable of storing information on an optical disc 2. The disc drive 1comprises a processing circuit 4 which, at an input 3, receivesinformation to be stored from an arbitrary source (not shown).

FIG. 2 illustrates the information received as a digital data stream 6,visualized as a “train” of bytes 7, which will also be indicatedhereinafter as data bytes Bd(α), α being an integer used as an index. Itis assumed that the “train” travels from left to right, and that thedata bytes arrive at the processing circuit 4 in the order Bd(1), Bd(2),Bd(3), etc, as indicated from the right to the left in FIG. 2.

The processing circuit 4 provides bytes to be written to reading/writingmeans 5, which perform the actual writing on disc 2. The reading/writingmeans 5 comprise rotating means for rotating the disc 2, laser means forgenerating an optical write beam, etc, as will be clear to those skilledin the art. Since such reading/writing means are known per se, it is notnecessary here to describe such reading/writing means in more detail.However, it is noted that the order in which the bytes are written ondisc is not the same as the order of the bytes as received by theprocessing circuit 4.

In the following, the order of byte writing will be explained, firstaccording to the existing BRD standard, later according to the methodproposed by the present invention. This explanation will be illustratedwith matrices, while bytes will be shown as occupying locations in sucha matrix. Such illustration is clarifying in the sense that it ispossible to implement an information-writing process by actually usingmatrix memories, indeed. However, it is to be understood that thematrices are used here merely as a tool for explanation, not necessarilyas a tool for implementation. In the end, the only thing that matters isthe byte writing order, and the knowledge of which bytes belong to whichcode word. Those skilled in the art are capable of designing aprocessing circuit such that it writes bytes in the desired order.

First, the processing circuit 4 performs a code word constructing step.

From the data bytes Bd received at input 3, the processing circuit 4first constructs code words 11 in accordance with a predetermined errorcorrection code. Although other error correction codes are possible, agenerally used and well-known error correction code is the Reed Solomoncode, and in the following it will be assumed that code words are inaccordance with this Reed Solomon code. The processing circuit 4receives a number Nd of data bytes (Nd being less than 248), andcalculates a number Ne of error correction bytes (Ne being 248 minusNd). Together, these Nd data bytes and the corresponding Ne errorcorrection bytes form one code word 11 having a length of 248 bytes, asillustrated in FIG. 3. For the following explanation, the exact valuesof Nd and Ne are not important. It is sufficient to mention that, if allNd data bytes and all Ne error correction bytes of a code word areavailable, it is possible to detect and correct some errors in this codeword; generally speaking, the more error correction bytes are added, themore bytes can be corrected.

An ECC block is defined from all bytes of a group of 304 of such codewords 11, without containing any byte of another code word. Thus, an ECCblock comprises 304×248=75 392 bytes.

In FIG. 4, an ECC block is visualized as a matrix 10, wherein the 304code words 11 are shown as colums 0, 1, 2, . . . 303, and wherein thebytes of these code words 11 are shown as 248 rows 0, 1, 2, . . . 247.Since each row in this matrix 10 contains exactly one code word, thismatrix will hereinafter be indicated as primary matrix.

The 75 392 elements of this primary matrix 10 are indicated hereinafteras elements e(ij), wherein i indicates a row number and j indicates acolumn number. With reference to FIG. 2, elements e(i=0-(Nd-1),0)correspond to data bytes Bd(α=1-Nd) of the first code word 11(0),elements e(i=0-(Nd-1),1) correspond to data bytes Bd(α=(Nd+1)-2Nd) ofthe second code word 11(1), etc. Elements e(i=Nd-247,0) correspond toerror correction bytes, which will be indicated as Be(β=1-Ne), β beingan integer used as an index.

From this primary matrix 10, a secondary matrix 20 having 152 columns of496 bytes is constructed, each column comprising the bytes of two codewords. This secondary matrix 20 is illustrated in FIG. 5. The elementsof this secondary matrix 20 will be indicated as f(k,l), wherein kindicates a row number and 1 indicates a column number. For each 1between 0 and 151, column 1 is filled by the bytes of code words 11(21)and 11(21+1), i.e. elements e(i=0-247,21) and e(i=0-247,21+1) of theprimary matrix 10. Elements e(i,21) of the primary matrix 10 are placedat location f(2i,1) of the secondary matrix 20, while elements e(i,21+1)of the primary matrix 10 are placed at location f(2i+1,1) of thesecondary matrix 20. Thus, the elements e(i,j) of the original 304×248ECC block matrix 10 are displaced to elements f(k,l) of the 152×496matrix 20, according to the following relationships:k=2i for j=0, 2, 4, 6, 8, . . . 302   (1a)l=j/2 for j=0, 2, 4, 6, 8, . . . 302   (1b)k=2i+1 for j=1, 3, 5, 7, 9, . . . 303   (1c)l=(j-1)/2 for j=1, 3, 5, 7, 9, . . . 303   (1d)

In a next step, a row shift operation is performed on the elementsf(k,l) of the 152×496 matrix 20 so as to obtain a 152×496 third matrix30 of which the elements will be indicated as g(m,n), as illustrated inFIG. 6. Rows 0 and 1 remain in place, the elements f(2,1=0-151) andf(3,1=0-151) of rows 2 and 3 are shifted 3 places to the left (i.e. tolocation g(m,n) with m=k and n=1-3), the elements f(4,1=0-151) andf(5,1=0-151) of rows 4 and 5 are shifted 6 places to the left (i.e. tolocation g(m,n) with m=k and n=1-6), etc. In general, for index i=0-247,the elements f(2i,l=0-151) and f(2i+1,1=0-151) of rows 2i and 2i+1 areshifted to locations g(m=k,n=1-3(i-1)). These shift operations arecyclic, which means that elements disappearing on the left are appendedon the right. This can be expressed by the formula n=MOD(1-3(i-1),152).

Thus, the elements in a certain row stay within this row, i.e. m=k forall elements.

The purpose of this row shift operation is to prevent bit slip, i.e. tohave all code words benefit from synchronization patterns written todisk, as will be clear to those skilled in the art.

In a next step, three BIS columns 41, each having 496 bytes, areintroduced into the third matrix 30 so as to obtain a 155×496 fourthmatrix 40 of which the elements will be indicated as h(p,q), asillustrated in FIG. 7.

The BIS-columns 41 are inserted at regular intervals, i.e. betweencolumns 37 and 38, between columns 75 and 76, and between columns 113and 114 of the third matrix 30. Each BIS column contains 8 code words of62 bytes each. Each code word consists of 30 data bytes and 32 paritybytes, so that the code words are very well protected against errors(better than the main data).

The BIS-columns 41 serve as a burst indicator (BIS=Burst IndicatorSubcode). On decoding, the BIS-columns are decoded first. If two or moresubsequent BIS symbols on the disc require correction, this is anindication for a burst error. This information is used to apply erasuresduring the correction of the main data code words, thus increasing thenumber of errors that can be corrected.

As was noted above, the BIS columns contain 24 code words of 62 byteseach. Like the main data, these code words are divided into segments,each segment containing one symbol of each code word. In a sixth step, acyclic row shift is applied to the elements of the BIS columns,similarly as described above with respect to the fourth step, in orderto protect all BIS-code words equally against bit slip.

As was noted above, the BIS code words consist of 30 data bytes and 32parity bytes. The 30 data bytes provide storage space for information.In other words, the BIS columns form an auxiliary data channel inparallel to the main data channel. Part of this auxiliary data channelis used to store addressing information. The ECC block is divided into16 groups, called sectors, of 31 rows each. Each sector contains oneaddress, which is stored in the BIS-columns of the first three rows(giving 9 symbols to store the addressing information)

If the BIS code words were divided straightforwardly into segments, asin the main data channel, all parity symbols would end up in theBIS-columns of the last 256 rows of the ECC block. This would leave noroom to store the addresses in the sectors contained in these rows.Instead, the symbols of the code words are divided into the segmentssuch that the first 6 rows of the initial 24×62 matrix end up in thefirst 3 rows of each sector. The parity symbols end up in the last 16rows of each sector. In other words, the symbols of the BIS code wordsare still divided into segments, but this is done in such a way that,for example, the first symbol of code word 1 may end up in the samesegment as the fifth symbol of code word 10. This has no implicationsfor the error correction capabilities since all symbols in a code wordare of equal importance.

The address information may be regarded as a matrix of 16×9 (one addressof 9 symbols for each of the 16 sectors in an ECC block). This matrixshould be copied to the first 6 rows of the initial 24×62 BIS matrix insuch a way that the addresses end up in the correct order in the firstthree rows of each sector after conversion of the 24×62 matrix to the3×496 matrix. This is called address pre-interleaving.

After the above-mentioned steps, the elements of the resulting matrixare written to disc row by row. In FIG. 8, a resulting track recordingof an ECC block is visualized as a longitudinal ribbon. This recordingcomprises 496 block segments 12(p), each block segment 12(p) containingthe 155 bytes of one row h(p,q=0-154). In other words, each code word11(j) has one byte e(i,j) in each group of two consecutive blocksegments 12(p) and 12(p+1). Consequently, the spatial distance betweentwo consecutive bytes e(i,j) and e(i+1,j) of one code word 11(j) isalways as large as possible. It can also be seen that it is not possibleto reconstruct all data bytes of all code words 11(j) until all blocksegments 12(p) of the ECC block have been read.

FIG. 9 schematically shows an SFFO disc 2 and a track recording of one64-kByte ECC block close to the inner radius of the disc. As illustratedin the Figure, the length of this ECC block on disc corresponds toalmost 2×360° track length, such that, over a substantial length, blocksegments in one track 13 a and block segments in the neighboring track13 b belong to one and the same ECC block. In the enlargement of FIG. 9,a random error 14 is shown. This random error 14 has small dimensions,but still the size of the random error 14 is such as to affect threeadjacent elements in track 13 a and three adjacent elements in track 13b. The three affected adjacent elements in track 13 a belong to threedifferent code words; the same applies to the three affected adjacentelements in track 13 b. However, it may happen that the block segmentsin neighboring tracks 13 a and 13 bare more or less aligned, such thatone of the three affected adjacent elements in track 13 a and one of thethree affected adjacent elements in track 13 bbelong to one and the samecode word, as illustrated in FIG. 9 for the elements indicated with anasterisk. Thus, this one random error 14 will cause two errors in onecode word. It will be clear that the same will apply to other elements,specifically to those elements immediately adjacent to the elementsindicated with an asterisk.

The present invention proposes an algorithm for calculating a new orderfor writing the bytes of code words 11, such that the writteninformation can be considered as constituting two ECC blocks of smallersize than the original ECC block 10. For explaining the general conceptof this invention, the new order for writing the 75 392 bytes of 304code words 11 will be described. The method of the present inventionresults in two 32-kByte ECC blocks, which also have the property ofburst indication and address pre-interleaving as described in the abovein respect of the state of the art.

Before explaining the present invention, an ECC block will be defined asa group of bytes which:

is written to disc as a closed group, i.e. the bytes are writtenconsecutively to disc;

contains a collection of all (data and error correction) bytes of acertain number of code words, i.e. the collection contains all bytes ofthese code words and does not contain any byte of other code words.

Thus, for being able to decode one code word, it is necessary to readthe entire group of 75 392 bytes, whereupon all 304 code words can bedecoded. It is noted that an ECC block remains an ECC block, even if theorder of the bytes is changed.

In the writing method of the state of the art, as described above, the248 bytes of each code word are distributed over substantially theentire group of 75 392 bytes of the first matrix 10, so that this groupconstitutes one ECC block of 64 kBytes. In the writing method proposedby the present invention, the 248 bytes of any one code word aredistributed over either the first half of the group or the second halfof the group. Then, for being able to decode one code word, it issufficient to read the corresponding half of the group only, whereupon152 code words can be decoded while the other 152 code words cannot bedecoded. Thus, in accordance with the invention, each half of the groupin itself fulfils the above definition of an ECC block, now a block of32 kBytes. In the following, these half groups will be indicated assmall ECC blocks, to make the distinction from the original 64-kByte ECCblock.

The present invention will be explained by first assuming that, in afirst phase (first and second steps), the processing circuit 4 hasconstructed 304 code words, using the same type of code (Reed Solomon)as the prior art, as described above and visualized by the 304×248primary matrix 10 of FIG. 4.

Next, a secondary matrix 120 having 152 columns of 496 bytes isconstructed, each column comprising the bytes of two code words. Thissecondary 152×496 matrix 120 is illustrated in FIG. 10. The elements ofthis secondary matrix 120 will be indicated as ff(r,s).

In the method of the prior art, as described with reference to FIG. 5, acolumn of the secondary 152×496 matrix 20 is formed by “zipping” twocode words into each other, i.e. alternatingly taking a byte from theone code word and a byte from the other code word. According to animportant aspect of the present invention, a column of the secondary152×496 matrix 120 is formed by placing two code words below each other.In principle, this may always be two code words adjacent to each otherin the primary matrix 10. In the preferred embodiment illustrated inFIG. 10, code word (s+152) is placed below code word s, s ranging from 0to 151. Thus, the elements e(i,j) of the original 304×248 ECC blockmatrix 10 are displaced to elements ff(r,s) of the 152×496 secondarymatrix 120, according to the following relationships:r=i for i=0-247 and j=0-151   (2a)s=j for i=0-247 and j=0-151   (2b)r=i+248 for i=0-247 and j=152-303   (2c)s=j-152 for i=0-247 and j=152-303   (2d)

Thus, it can be seen that, for example, element e(0,152) is displaced toelement ff(248,0).

In a next step, a cyclic row shift operation is performed on theelements ff(r,s) of the 152×496 secondary matrix 120 so as to obtain a152×496 third matrix 130 of which the elements will be indicated asgg(t,u), as illustrated in FIG. 11. Row 0 remains in place, the elementsff(1,s=0-151) of row 1 are shifted 3 places to the left (i.e. tolocation gg(1,u) with u=s-3), the elements ff(2,s=0-151) of row 2 areshifted 6 places to the left (i.e. to location gg(2,u) with u=s-6), etc.In general, for index r=0-495, the elements ff(r,s=0-151) of row r areshifted to locations gg((t,u) of the 152×496 third matrix 130, accordingto the following relationships:t=r   (3a)u=MOD(1-MOD(3*MOD(m,248),152)+152,152)   (3b)

It is noted that all elements in a certain matrix row stay within thisrow, i.e. t=r for all elements.

In a next step, three BIS columns 41, each having 496 bytes, areintroduced into the third matrix 130 so as to obtain a 155×496 fourthmatrix 140 of which the elements will be indicated as hh(v,w), asillustrated in FIG. 12.

This operation is similar to the operation described with reference tothe prior art.

As was noted above, the BIS columns may be regarded as a 24×62 matrix,and the address information may be regarded as a 16×9 matrix (oneaddress of 9 symbols for each of the 16 sectors in an ECC block). In theprior art, the 16×9 address matrix is copied to the first 6 rows of theinitial 24×62 BIS matrix in such a way that the addresses end up in thecorrect order in the first three rows of each sector after conversion ofthe 24×62 matrix to the 3×496 matrix. According to the presentinvention, the 24×62 BIS matrix is divided into two 12×62 BIS-matrices.The addresses of the first 8 sectors are pre-interleaved into the first6 rows of the first 12×62 BIS matrix. The addresses of the last 8sectors are pre-interleaved into the first 6 rows of the second 12×62BIS matrix. Then, the two 12×62 BIS matrices are each interleaved into aseparate 3×248 matrix so as to form the BIS columns in a way similar tothe way as described above for the larger BIS matrices. The first 3×248matrix is inserted into the first small ECC block, the second 3×248matrix is inserted into the second small ECC block.

All in all, when the bytes of the 24×62 BIS matrix are indicated asb_(BIS)(N,C), wherein C indicates the BIS code words (C=0-23), andwherein N indicates the symbols in the code words (N=0-61), these bytesare placed in unit uu, row rr and column cc in accordance with thefollowing formulas:uu=MOD({DIV(N,2)+4−DIV(MOD(C,12),3)},4)+4*MOD(N,2)+8*DIV(C,12)   (4a)rr=DIV(N,2)   (4b)cc=MOD({C+30−DIV(N,2)},3)   (4c)

Furthermore, when the bytes of the 16×9 address matrix are indicated asAF(x,y), wherein y indicates the address words (y=0-15), and wherein xindicates the symbols in the address words (x=0-8), these bytes areplaced in row rrr and column ccc in accordance with the followingformulas:rrr=2*DIV(x,3)+DIV({MOD(y,8)},4)   (5a)ccc=3*MOD({DIV(x,3)+16−y},4)+MOD({x+DIV(x,3)},3)+12*DIV(y,8)   (5b)

The row shift operation illustrated in FIG. 11 does not displace amatrix element ff(r,s) from one row to another. The same applies to theinsertion of BIS columns as illustrated in FIG. 12. The same appliesalso to the interleaving operation of the BIS matrix and the addressmatrix, but these operations are not illustrated. Thus, it is possibleto reconstruct all data bytes of the first 152 code words as soon as thefirst 248 block segments 112 have been read. Similarly, it is possibleto reconstruct all data bytes of the second 152 code words as soon asthe second 248 block segments 112 have been read. Therefore, since theprimary matrix, in accordance with the present invention, has beendefmed by placing two code words below each other, the upper half ofmatrix 120 may be considered as a small ECC block 121 a containing thecode words 0 to 151, and the lower half of matrix 120 may be consideredas a small ECC block 121 b containing the code words 152 to 303. Now ifthe elements hh(v,w) of this matrix 140 are written by first writing theelements hh(0,0), hh(0,1), hh(0,2), . . . hh(0,154) of the first row,then writing the elements hh(1,w=0-154) of the second row, then writingthe elements hh(2,w=0-154) of the third row, etc, the resultingrecording is visualized in FIG. 13, where the recording is shown as alongitudinal ribbon, comparable to FIG. 8. A collection of 155 elementshh(v,w=0-154) will be indicated as block segment 112(v). The recordingcomprises 496 of such block segments 112, each block segment 112containing one byte of 152 of the code words 11. Consequently, thespatial distance between two bytes hh(v,w) and hh(v+1,w) of one codeword has decreased by a factor two.

FIG. 14 is a drawing similar to FIG. 9, now illustrating the recordingof matrix 140, and also illustrating the effect of a random error 14 onthe recording of matrix 140. When comparing FIG. 14 with FIG. 9, it canbe seen that the total length of recording 140 is equal to the totallength of recording 10. However, the length of the recording of a smallECC block 141 a, 141 b (corresponding to small ECC blocks 121 a, 121 b,respectively, after row shift and introduction of BIS columns) is nowshorter than the track length. If a random error 14 now affects twobytes in two adjacent tracks 113 a, 113 b, these two bytes will belongto different small ECC blocks 141 a, 141 b and, hence, will belong todifferent code words. Thus, the same random error 14 now only results ina maximum of one error in any code word.

It is noted that, as compared with the state of the art, the size of theECC blocks has been reduced. Normally, a reduction of ECC block sizeresults in a reduction of the effective correction capacity for bursterrors. This is also true in the case of the present invention, when theeffective error correction capacity of the method proposed by theinvention for an SFFO disc is compared with the prior art method appliedto a BRD disc. However, when the prior art method is applied to an SFFOdisc, the effective error correction capacity is already reduced due tothe fact that one ECC block occupies about two tracks. Taking thissituation as a starting point, the reduction of ECC block size asproposed by the invention does not result in any further reduction inthe effective correction capacity.

In the above, the present invention has been explained on the basis of304 code words, in order to facilitate a comparison with the state ofthe art, which is also based on 304 code words. However, as explained,the matrix 120 may also be considered as a combination of two small ECCblocks, embodied by rows 0 to 247 and rows 248 to 495, respectively.Therefore, it is not necessary to manipulate 304 code words, but it ispossible to manipulate just 152 code words. In other words, according tothe present invention it is possible to define an ECC block 121 a andimplement the inventive concept of the present invention as soon as 152code words have been received. This may reduce the required amount ofmemory space.

FIG. 15 illustrates schematically how a byte writing order in accordancewith the present invention can be determined.

First, Nd data bytes are collected, and a code word 11 containing 248bytes is defined by calculating Ne=248 -Nd error correction bytes, asdescribed above.

In a next step (1), 152 of such code words are placed in a primarymatrix M1 having 152 columns and 248 rows, elements of this primarymatrix M1 being indicated as m1(i,j). Thus, byte i of code word j isplaced at location m1(i,j).

In a next step (2), a cyclic row shift is performed, yielding a secondmatrix M2 having 152 columns and 248 rows, elements of this secondmatrix M2 being indicated as m2(t,u). Thus, element m1(i,j) of the firstmatrix M1 is placed at location m2(t,u) according to formulas:t=iu=MOD(j-MOD(3*i,152)+152,152)

In a next step (3), this second matrix M2 is transformed into a thirdmatrix M3 having 155 columns and 248 rows, elements of this second thirdmatrix M3 being indicated as m3(v,w), in order to create space for BIScolumns. The transformation is such that element m2(t,u) of the secondmatrix M2 is placed at location m3(v,w) according to formulas:v=tw=u+DIV(u,38)

The steps (4), (5), and (6) illustrate the definition and insertion ofBIS columns.

First, 8 addresses are defined, each having 9 bytes, and these 8addresses are placed in an address matrix AF having 8 columns and 9rows, elements of this address matrix AF being indicated as AF(x,y).Thus, byte y of address x is placed at location AF(x,y).

Also, 12 BIS code words are defined, each having 62 bytes, and these 12BIS code words are placed in a BIS matrix BIS having 12 columns and 62rows, elements of this BIS matrix being indicated as b_(BIS)(n,c).

Then a step (4) of address pre-interleaving is performed, whereinaddress bytes AF(x,y) are placed in the BIS matrix at locationsb_(BIS)(n,c) according to formulas:n=2*DIV(x,3)+DIV(y,4)c=3*MOD({DIV(x,3)+8−y},4)+MOD({x+DIV(x,3)},3)

Then, in a step (5), the 12×62 BIS matrix BIS is transformed into asecond BIS matrix B2 having 3 columns and 248 rows, elements of thissecond BIS matrix B2 being indicated as b₂(r,s), wherein BIS bytesbBIs(n,c) are placed in the second BIS matrix B2 at locations b₂(r,s)according to formulas:

uu=MOD({DIV(n,2)+4−DIV(c,3)},4)+4*MOD(n,2)rr=DIV(n,2)r=31*uu+rrs=MOD({c+30−DIV(n,2)},3)

Hereinafter, each column of this second BIS matrix B2 will also beindicated as a BIS line BL(s) comprising 248 BIS bytes.

Then, in a step (6), the 3 columns of this second BIS matrix B2 areinserted into the third matrix M3, wherein B2 bytes b₂(r,s) are placedin the third matrix M3 at location m3(v,w) according to formulas:w=39*s+38v=r

It is noted that address bytes AF(x,y) are placed in the third matrix M3at location m3(v,w) according to formulas:w=39*MOD(y,3)+38v=31*x+DIV(y,3)

Then the 38440 elements of this third matrix M3 are written in arow-by-row fashion. This can be expressed by the following formulaB(x)=m3(DIV(x,155),MOD(x,155)), wherein:B(x) indicates the x-th byte to be written, x being an index rangingfrom 0 to 38439. Thus, B(0)=m3(0,0),B(1)=m3(0,1),B(2)=m3(0,2), . . .B(155)=m3(1,0), . . . B(38439)=m3(247,154).

It is noted that the re-ordering steps which are described above as anumber of subsequent matrix transformations actually need not beperformed as subsequent transformation steps. It should be clear thatthe overall re-ordering process can be considered as one matrixtrrmsformation from an input 152×248 matrix M1 to an output 155×248matrix M3, characterized by a unique transformation relation between thecoordinates (i,j) of input matrix elements ml (i,j) and the coordinates(v,w) of output matrix elements m3(v,w). In other words, the coordinates(v,w) of output matrix elements m3(v,w) can be expressed as functionsv(i,j) and w(i,j), which functions can be stored in a memory 8 ofprocessing circuit 4, for example as lookup tables. Similarly, a uniquetransformation relation exists between the coordinates b_(BIS)(n,c) ofthe BIS matrix BIS and the coordinates (v,w) of output matrix elementsm3(v,w).

Furthermore, it is of course possible that the processing circuit 4actually constructs an output 155×248 matrix M3 having output matrixelements m3(v,w) and stores this matrix in an associated memory, andthat the processor circuit 4 during a writing phase reads the elements,row by row, from this output 155×248 matrix M3. In fact, this is onepossible, practical implementation. However, this is not necessarily theonly possible implementation. The only important aspect is that theprocessing circuit 4 collects 152×Nd data bytes, calculates 152×Ne errorcorrection bytes, calculates 12×62 BIS bytes, and transfers thecollection of 38 440 bytes to the writing means 5 in the correct,predetermined order. In other words, the processing circuit 4 may beprogrammed in any way ensuring that it knows whether output byte ξ,ξ=0-38439, is one of the Nd data bytes, one of the error correctionbytes, or one of the BIS bytes, and furthermore knows which one of saidbytes.

The disc drive device 1 can also read data from disc 2. In a readingphase, the reading/writing means 5 read bytes from the disc 2, andprovide the bytes thus read to the processing circuit 4, which may storethe bytes in a 155×248 matrix M3. Then, in a reconstruction phase, theprocessing circuit 4 may reconstruct a 152×248 ECC block having elementse(i,j), using the same formulas as mentioned above. More particularly,for each value of index i and j, the process circuit 4 reads thecorresponding byte at location m3(v,w) as defined by the above-mentionedformulas. If necessary, the process circuit 4 corrects possible errorsfor each code word 11 of this small ECC block formed by matrix M1 withelements e(i,j), using the error correction bytes. Now the processingcircuit 4 can output the data bytes 7 at its output 9.

It should be clear to those skilled in the art that the presentinvention is not limited to the exemplary embodiments discussed above,but that various variations and modifications are possible within theprotective scope of the invention as defined in the appended claims.

For example, although the present invention has been described againstthe background of the BRD standard, and the present invention isexplained in the above for this specific example, the inventive conceptof the present invention is also applicable if other standards are usedas a starting point. Minor modifications may be necessary to adapt theexemplary method as described above to such a different standard, aswill be clear to those skilled in the art.

Furthermore, although the present invention has been devised with a viewto solving problems associated with circular record media, theinformation-writing method proposed by the invention may also be appliedwhen writing information to linear media.

1. Method of writing information to a record medium, wherein 152 codewords [11(j)] each having 248 bytes [m1(i,j)] and 12 BIS words eachhaving 62 BIS bytes [b₂(r,s)] are combined so as to form an ECC block(M3) having 38440 elements [m3(v,w)], which elements are consecutivelywritten to said medium.
 2. Method of writing information to a recordmedium, comprising the following steps: (a) calculating a predeterminednumber (Ne) of error correction bytes (Be) on the basis of apredetermined number (Nd) of data bytes (Bd) so as to form a code word(11) of 248 code word bytes; (b) repeating step (a) until 152 of saidcode words [11(j)]have been formed, each comprising 248 code word bytes[m1(i,j)], j representing an index ranging from 0 to 151, i representingan index ranging from 0 to 247; (c) generating 3 BIS lines [BL(s)] eachcomprising 248 BIS bytes [b₂(r,s)], s representing an index ranging from0 to 2, r representing an index ranging from 0 to 247; (d) writing thecombination of 152×248 code word bytes [m1(i,j)] and 3×248 BIS bytes[b₂(r,s)] in an order obtainable by: (d1) placing the 152 code words[11(j)] as columns in a 152×248 first matrix (Ml) having first matrixelements [m1(i,j)]; (d2) performing a predefined cyclic row shiftoperation on this first matrix (M1) so as to obtain a 152×248 secondmatrix (M2) having second matrix elements [m2(t,u)]; (d3) placing thesecond matrix elements [m2(t,u)] of this second matrix (M2) at location[m3(v,w)] of a 155×248 third matrix (M3) in accordance with thefollowing formulas:v=tw=u+DIV(u,38) (d4) placing the BIS bytes [b₂(r,s)] at location [m3(v,w)]of said 155×248 third matrix (M3) in accordance with the followingformulas:v=rw=39*s+38 (d5) writing the elements [m3(v,w)] of said 155×248 thirdmatrix (M3) in a row-by-row fashion in accordance with the followingformula:B(ξ)=m3(DIV(ξ,155),MOD(ξ,155)), whereinB(ξ) indicates the ξ-th byte to be written, ξ being an index rangingfrom 0 to 38
 439. 3. Method according to claim 2, wherein said cyclicrow shift is performed in accordance with the following formulas:t=iu=MOD(j-MOD(3*i,152)+152,152)
 4. Method according to claim 2, furthercomprising the steps of: generating 12 BIS code words, each having 62BIS bytes [b_(BIS)(n,c)], c representing an index ranging from 0 to 11,n representing an index ranging from 0 to 61; and generating said 3 BISlines [BL(s)] by combining 4 of said BIS code words so as to form a BISline.
 5. Method according to claim 4, wherein a relationship betweensaid BIS bytes [b₂(r,s)] of said 3 BIS lines [BL(s)] on the one hand andsaid BIS bytes [b_(BIS)(n,c)] of said 12 BIS code words on the otherhand complies with the following formulas:b₂(r,s)=b_(BIS)(n,c) , with:s=MOD({c+30−DIV(n,2)},3) and r=31*uu+DIV(n,2), whereinuu=MOD({DIV(n,2)+4−DIV(c,3)},4)+4*MOD(n,2)
 6. Method according to claim4, further comprising the steps of: generating 8 address words eachhaving 9 address bytes [AF(x,y)], x representing an index ranging from 0to 7, y representing an index ranging from 0 to 8; putting said addressbytes [AF(x,y)] into said 12 BIS code words, wherein a relationshipbetween said address bytes [AF(x,y)] of said address words on the onehand and said BIS bytes [b_(BIS)(n,c)] of said 12 BIS code words on theother hand complies with the following formulas:b_(BIS)(n,c)=AF(x,y) with:n=2*DIV(x,3)+DIV(y,4)c=3*MOD({DIV(x,3)+8−y},4)+MOD({x+DIV(x,3)},3)
 7. Method of readinginformation from a record medium, wherein an ECC block (M3) having 38440 elements [m3(v,w)] is read, from which 152 code words [11(j)] eachhaving 248 bytes [ml(i,j)]and 12 BIS words each having 62 BIS bytes[b₂(r,s)] are reconstructed.
 8. Method of reading information from arecord medium, comprising the following steps: (a) reading 38 440consecutive bytes [B(ξ)], ξ representing an index ranging from 0 to38439; (b) reconstructing 152 code words [11(j)] from said read bytes[B(ξ)], each code word comprising 248 code word bytes [ml(i,j)], jrepresenting an index ranging from 0 to 151, i representing an indexranging from 0 to 247; wherein a relationship between said code wordbytes [ml(i,j)] on the one hand and said read bytes [B(ξ)] on the otherhand complies with the following formulas: m1(i,j)=B(ξ), with ξ=i*155+u+DIV(u,38) wherein u=MOD(j-MOD(3*i,152)+152,152)
 9. Methodaccording to claim 8, wherein, the 248 bytes are submitted to an errorcorrection processing in each code word [11(j)] thus reconstructed; andwherein a predetermined number (Nd) from among the corrected bytes areoutputted as data bytes (Bd).
 10. Method according to claim 8, furthercomprising the step of reconstructing 12 BIS words from said read bytes[B(ξ)], each BIS word comprising 62 BIS bytes [b_(BIS)(n,c)]; crepresenting an index ranging from 0 to 11, n representing an indexranging from 0 to 61; wherein a relationship between said BIS bytes[b_(BIS)(n,c)] on the one hand and said read bytes [B(ξ)] on the otherhand complies with the following formulas:b_(BIS)(n,c)=B(ξ), with ξ=r*155+39*s+38 wherein:s=MOD({c+30-DIV(n,2)},3)r=31*uu+DIV(n,2) with uu=MOD({DIV(n,2)+4-DIV(c,3)},4)+4*MOD(n,2) 11.Method according to claim 10, further comprising the step ofreconstructing 8 address words from said reconstructed BIS words, eachaddress word comprising 9 address bytes [AF(x,y)]; x representing anindex ranging from 0 to 7, y representing an index ranging from 0 to 8;wherein a relationship between said address bytes [AF(x,y)] on the onehand and said BIS bytes [b_(BIS)(n,c)] on the other hand complies withthe following formulas:AF(x,y)=b_(BIS)(n,c), with n=2*DIV(x,3)+DIV(y,4)c=3*MOD({DIV(x,3)+8-y},4)+MOD({x+DIV(x,3)},3)
 12. Informationrecording/reading apparatus (1) designed to write information to arecord medium (2) in accordance with any of claims 1-6, or to readinformation from a record medium (2) in accordance with claim 7,respectively.
 13. Record carrier (2) containing information written by amethod in accordance with claim 1.